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8 Pin Robert Noyce Integrated Circuit Chip 74HC595D Parallel Out Shift Register

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8 Pin Robert Noyce Integrated Circuit Chip 74HC595D Parallel Out Shift Register

Brand Name : NXP
Model Number : 74HC595D
Certification : Original Factory Pack
Place of Origin : Malaysia
MOQ : 20pcs
Price : Negotiation
Payment Terms : T/T, Western Union,PayPal
Supply Ability : 4500PCS
Delivery Time : 1 Day
Packaging Details : please contact me for details
FEATURES : Designed and qualified for industrial level
FEATURES2 : 8-bit serial input
FEATURES3 : 8-bit serial or parallel output
FEATURES4 : Storage register with 3-state outputs
FEATURES5 : Shift register with direct clear
FEATURES6 : 100 MHz (typ) shift out frequency
FEATURES7 : Output capability: – parallel outputs; bus driver – serial output; standard
FEATURES8 : ICC category: MSI.
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8 Pin Robert Noyce Integrated Circuit Chip 74HC595D Parallel Out Shift Register


FEATURES

• 8-bit serial input

• 8-bit serial or parallel output

• Storage register with 3-state outputs

• Shift register with direct clear

• 100 MHz (typ) shift out frequency

• Output capability: – parallel outputs; bus driver – serial output; standard

• ICC category: MSI.


APPLICATIONS

Serial-to-parallel data conversion

• Remote control holding register.


DESCRIPTION

The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.


The “595” is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks.


Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.


The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.


Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑(CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V


2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V.


SYMBOLPINDESCRIPTION
Q0 to Q715, 1 to 7parallel data output
GND8
Q79serial data output
MR10master reset (active LOW)
SHCP11shift register clock input
STCP12storage register clock input
OE13output enable (active LOW)
DS14serial data input
VCC16positive supply voltage

DC CHARACTERISTICS FOR 74HCT


For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI.


Note to HCT types


The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.


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